1. Field of the Invention
The present invention relates to digital computing. More particularly, the present invention relates to a method and apparatus for one or more monitors that detects and reports a status event to a database. Additionally, the present invention relates to an apparatus and method that reports multiple status events to a database through a single program. Additionally, the present invention relates to a monitor language that describes status events using a plurality of keywords.
2. Description of the Related Art
A digital design performs a finite number of logical functions or operations. For instance, a typical digital design such as a microprocessor might support four separate operations called addition (a), multiplication (m), subtraction (s), and division (d). Within each operation, different specific events may occur. For instance, addition of two negative numbers may occur, or addition of two positive numbers may occur.
A digital design will support many combinations of events where each type of specific event is called a state. In more complex designs, events may happen serially so that the number of states is increased. For instance, the operation sequence addition-multiplication-division (amd) is a different state than the operation sequence addition-multiplication-subtraction (ams). More states exist in the digital design when each a, m, s, and d operation supports various types of operands (i.e., positive, negative, and zero). Each permutation combining possible specific events results in a different state.
Exhaustive verification of modern digital designs such as microprocessors is virtually impossible because such designs may attain an almost incalculable number of states. A designer must therefore determine a sub-list of states that represent the most interesting states. The sub-list of states should include functional events, which are events that can be defined based on the specification of the design, and implementation events, which are specific to how the designer chose to implement the specification. While the sub-list of interesting states is not exhaustive, it usually provides a yardstick for measuring test coverage. To gain an adequate level of confidence that the design is functioning correctly, it is necessary to verify whether the design attains all of these interesting states during operation or simulation.
Verification of digital designs is usually done using a simulator. A simulator is a program that runs the design file of a digital design in order to recreate how the design would perform on a computer chip. A common method for generating test stimulus is to use a random, or directed random, test case generator. With random test case generation, the correctness of the design being simulated is established by having the results predicted automatically by some sort of reference model. The actual checking may take many forms, ranging from comparing the final results in memory to checking internal state cycle-by-cycle. There are major advantages to using random test case generation. Computer programs can generate test cases much faster than people can, so many more design states can be reached in the same amount of time using random test case generation. This is critically important for complex designs which need a reasonable time-to-market. Also, by introducing randomness, the verification engineer can think of a general set of tests that would hit interesting states, and let the computer generate all the special cases. In many cases, the random test generator ends up creating situations that a tester may not have thought to create.
A drawback to random test case generation, however, is that it is difficult to know exactly what is being tested. Thus, it is difficult to gain an adequate level of confidence that the design is attaining all of the required states determined by the designer to be interesting. A number of approaches have been used to determine when a design has been sufficiently verified using random test case generation. One method is to use statistical data from previous designs to predict the expected bug rate. This requires that the statistical data exist for the same style of design and the same test generation tool. Another method is to simply try as many different test strategies with the random test generator as one can think of, and then run them until the bug rate decreases. A third method is to use coverage analysis tools to quantify what percentage of the existing design states have been hit.
Existing coverage analysis tools typically traverse the source code of the design to generate a list of unique states to be tracked. Since the resulting coverage data is based purely on the existing source code, the coverage data is very specific to the implementation of the design. There is no way to use the coverage data to evaluate functional coverage, or how much of the specification has been tested. It can also be difficult to evaluate how many of the cases that have not been hit are actually interesting. And finally, source-code generated coverage data can not include data on interesting combinations of events.
The present invention introduces a method for evaluating coverage from either a functional or an implementation perspective, including combinatorial coverage. It provides an easy way to write a software monitor to identify an event in a design and then log the information concerning attainment of the state into a database for further analysis. The analysis of the database will determine if adequate coverage is being performed on this list of events, and if not, the cause of the lack of coverage can be investigated. The list of events can be driven by the sub-list of events determined by the designer to be interesting.
The lists of interesting events in the test coverage of a design can, in some cases, be described by taking a cross product of some combination of events. For example, it is typically interesting to verify that the design has been tested where all combinations of two instructions have run back-to-back. Another example is to test all possible combinations of operands for an instruction. As designs are capable of executing more unique instructions with more types of operands, more interesting states can be expressed as a cross product of different events.
Supporting a new logic design style requires the invention of new coding techniques to verify the computer-aided design of the logic circuits and their constituent subcircuits. The N-nary logic design style is no exception. N-nary logic is a dynamic logic design style fully described in a copending patent application, U.S. patent application Ser. No. 09/019,355, filed 5 Feb. 1998 (5 Feb. 1998), now U.S. Pat. No. 6,066,965, and titled “Method and Apparatus for a N-Nary logic Circuit Using 1-of-4 Signals”, which is incorporated by reference for all purposes and is referred to as “The N-nary Patent.” The simulation of N-nary logic is fully described in the following copending patent applications: U.S. patent application Ser. No. 09/405,618, filed 24 Sep. 1999 (24 Sep. 1999), titled “Software Modeling of Logic Signals Capable of Holding More Than Two Values”, and U.S. patent application Ser. No. 09/405,474, filed 24 Sep. 1999 (24 Sep. 1999), titled “Multiple-State Simulation for Non-Binary Logic”, both of which are incorporated by reference for all purposes.
The N-nary logic family supports a variety of signal encodings, including 1-of-4. In 1-of-4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values, as is demonstrated in Table 1. In Table 1, the A0 and A1 wires are used to indicate the four possible values for operand A: 00, 01, 10, and 11. Table 1 also shows the decimal value of an encoded 1-of-4 signal corresponding to the two-bit operand value, and the methodology by which the value is encoded using four wires.
TABLE 1N-nary (1-of-4)2-bitSignal AN-nary (1-of-4) Signal Aoperand valueDecimal Value1-of-4 wires assertedA1A0AA[3]A[2]A[1]A[0]0000001011001010201001131000
“Traditional” dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, as shown in Table 1, N-nary logic only requires assertion of one wire. The benefits of N-nary logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of the N-nary Patent. All signals in N-nary logic, including 1-of-4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (0-3 inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a valid 1-of-N signal. Similarly, N-nary logic requires that a high voltage be asserted on only one wire for all values, even the value for zero (0).
Any one N-nary logic gate may comprise multiple inputs and/or outputs. In such a case, a variety of different N-nary encodings may be employed. For instance, consider a gate that comprises two inputs and two outputs, where the inputs are a 1-of-4 signal and a 1-of-2 signal and the outputs comprise a 1-of-4 signal and a 1-of-3 signal. Variables such as P, Q, R, and S may be used to describe the encoding for these inputs and outputs. One may say that one input comprises 1-of-P encoding and the other comprises 1-of-Q encoding, wherein P equals two and Q equals four. Similarly, the variables R and S may be used to describe the outputs. One might say that one output comprises 1-of-R encoding and the other output comprises 1-of-S encoding, wherein R equals four and S equals 3. Through the use of these, and other, additional variables, it is possible to describe multiple N-nary signals that comprise a variety of different encodings.
The signal naming convention used in the present disclosure is fully described in a copending patent application, U.S. patent application Ser. No. 09/210,408, filed 11 Dec. 1998 (11 Dec. 1998), now U.S. Pat. No. 6,289,497, and titled “Method and Apparatus for N-nary Hardware Description Language”, which is incorporated by reference for all purposes and is referred to as “The Hardware Description Patent.”
The signal naming convention identifies certain information that characterizes the signal, specifically information concerning 1-of-N degree, evaluation, and clock phase. The naming convention indicates the 1-of-N degree for each gate signal. The character, H, h, L, or l, in the evaluation field conveys information concerning the evaluation direction and evaluation completeness of the signal. The characters “H” and “h” indicate evaluation on the rising edge, or high-going signals; the characters “L” and “l” indicate evaluation on the falling edge, or low-going signals. This signal convention allows the transistor synthesis tool described in the Hardware Description Patent to ensure that only high-going signals are used for connections between gates. The transistor synthesis tool uses low-going signals internally within cells.
The use of the upper- and lower-case of H and L designate the “evaluation completeness” of the named signal. To understand “evaluation completeness,” a background discussion of N-nary signal characteristics may be helpful. A I-of-N signal is a signal driven by a cell that evaluates for all possible legal combinations of input. The 1-of-N signal will, if it fails to evaluate, represent an invalid state. A 0-or-1-of-N signal is a signal driven by a cell that fails to evaluate for some legal input value. The 0-or-1-of-N signal will, if it fails to evaluate, represent a null value. This stems from the fact that, even for a value of zero, a 1-of-N signal must assert a positive voltage on one, and only one, wire of the N potential wires. Failure of a 0-or-1-of-N signal to assert a wire during an evaluation clock phase therefore results in a null value, rather than a value of zero. In the preferred embodiment of N-nary C, 1-of-N signals are indicated by the upper-case characters H and L in the evaluation field; 0-or-1-of-N signals are indicated by the lower-case characters h and l in the evaluation field.
The value of the clock phase field delivers information regarding the clock phase during which evaluation of the cell driving the signal evaluates. The minimum valid value for phase is 0 and the maximum is M−1, where M is the highest number of clock phases available to the circuit under design. The number of valid clock phases is a design specific variable, but may typically be between 3 and 6.
N-nary C also allows certain other optional information to be included in the name of a signal, including a description of the signal and bit number information. In the preferred embodiment, the signal description is set forth in the descriptor field and may comprise any number of lower-case alphanumeric characters, including the underscore “_” character. The contents of the bit field specify the bit column to which the gate being constructed belongs. Generally, in a data flow design, all the gates that operate on a given bit of data (e.g., “bit 4”) are “floorplanned” such that the gates line up in a column (a “bit column”), facilitating orderly operation of the gates. The “floorplan” thus contains columns of related gates.